1. Field of the Invention
The present invention relates to a method for forming gate patterns in parallel on a photoresist layer, a method for manufacturing a semiconductor device having gate patterns in parallel, and a phase shift photomask used in such a forming method and such a semiconductor device manufacturing method.
2. Description of the Related Art
Generally, in semiconductor manufacturing processes, photolithography technology by photomasks has been used.
In the photolithography technology, a resolution limit for defining a dimension of a minimum pattern such as a gate pattern depends upon a wavelength of exposure light. Generally, since it is difficult to form gate patterns having a smaller dimension than a half wavelength of the exposure light, various high resolution techniques have been developed. One approach is a phase shift photomask such as a Levenson-type phase shift photomask where two transmitted light components opposite in phase from two openings are compensated for in a so-called phase edge which corresponds to one gate pattern (see: JP-57-62052-A).
In a first prior art method for manufacturing a semiconductor device where first and second groups of gate electrodes are arranged perpendicular to each other, a phase shift photomask and a trim photomask for trimming unnecessary phase edges are used (see: JP-2003-168640-A). This will be explained later in detail.
In the above-described first prior art manufacturing method, however, since the first group of gate electrodes are perpendicular to the second group of gate electrodes, if the integration is enhanced, the same phase light components may become closer to each other below gate patterns, which would reduce the resolution limit of the gate electrodes.
In a second prior art method for manufacturing a semiconductor device where all gate electrodes are arranged along one direction, a phase shift photomask and a trim photomask for the trimming unnecessary phase edges are also used (see: 2003-168640-A). This also will be explained later in detail.
In the above-described second prior art manufacturing method, since all the gate electrodes are arranged in parallel to each other, if the integration is further enhanced, the same phase light components hardly become closer to each other below gate patterns, which would not reduce the resolution limit of the gate electrodes.